The present invention is directed to a semiconductor package and, more particularly, to a lead frame and substrate based multi-chip module.
Semiconductor device packaging fulfills basic functions such as providing electric connections and protecting the die or chip against mechanical and environmental stresses. Continuing progress in reduction of the size of semiconductor dies allows for reducing package size. However, the increased functionality and complexity of the circuits integrated in the dies requires increased external connections, which increases the complexity of reducing the package size.
Semiconductor dies typically are encapsulated for surface mounting. Such surface mount devices often include more than one embedded or encapsulated die. The electrical contacts for connection with external circuits are exposed on either the sides and/or the bottom of the package and connected internally with electrical contact pads on the semiconductor die. The contacts of the exposed device may be a ball grid array (BGA) or a land grid array (LGA), for example. Various techniques are available for connecting the exposed electrical contacts of the package with the internal contacts of the embedded semiconductor die.
Minimum values are specified for the size of the individual exposed electrical contact surfaces of the device and for the spacing between adjacent electrical contact surfaces. Such specifications necessitate a compromise between the overall size of the packaged device and the number of individual electrical contact surfaces.
It is desirable to have a high density input/output package. It also is desirable to design and construct a package using available techniques that is able to increase inputs and outputs for a leaded package platform on a single package footprint.